This invention relates generally to techniques for the fabrication of integrated circuitry. More particularly, the invention relates to an improved construction for bipolar transistors in integrated circuits.
By way of general background, in bipolar transistors two types of current carriers, electrons and "holes," are involved in the conduction mechanism of the device. This is to be contrasted with unipolar devices, in which only a single carrier type is predominantly involved. A bipolar integrated circuit typically comprises many interconnected bipolar transistors, each of which is a three-terminal device having a base region, a collector region and an emitter region. There is one semiconductor junction between the base and emitter regions, and another junction between the base and collector regions. The collector and emitter regions of a transistor are doped with impurities that are of the same conductivity type, n-type or p-type, and the base region is of the opposite conductivity type. The transistor is then said to be of the n-p-n or the p-n-p type. The theory of operation of bipolar transistors is well known and will not be discussed in this specification.
In the fabrication of integrated circuits, many transistors are formed simultaneously, together with an isolation structure formed between adjacent transistors to prevent any unintended interaction between the devices. The isolation may, for example, take the form of a region of silicon dioxide, which is a conveniently available electrical insulator if the semiconductor materials comprise silicon. During the fabrication process, all of the base regions are formed in a single process step or related sequence of steps. Likewise, all of the emitter regions are formed in one step or series of steps, and there is typically a final metallization step in which electrical connections are made to the terminals of the transistors, by means of a patterned layer of metal formed over the circuit.
The formation of layers and patterned regions on an integrated circuit is effected by a variety of conventional process steps. Desired patterns are usually formed by means of photolithographic techniques, used in conjunction with patterned masks. The degree of precision with which the masks can be aligned with the circuit being fabricated typically limits the minimum feature geometry of the circuit. In a process having a number of such alignment steps, circuit features less than a few microns in width are difficult to achieve with consistency. It is therefore always desirable to reduce the number of photolithographic steps in the overall process, so that the complexity and cost of the technique can be minimized, and the circuits can be scaled down without affecting the yield of acceptable circuits resulting from the process.
In conventional bipolar transistor fabrication processes, at least two photolithographic operations are involved. The sequence of operations may vary from one process to another, but two photolithographic steps are almost invariably needed. Typically, one such step is employed to define the locations of emitter regions and the other is to define the locations of base contacts. A further photolithographic operation is usually required to define the areas of metallization over the circuit.
A significant limitation of conventional bipolar fabrication is the high-frequency performance of the resulting circuitry. It is well known that there are certain circuit parameters of bipolar transistors that affect the speed of operation and performance at high frequencies. Two of the most significant of these parameters are the base resistance and the base-collector capacitance. Reduction of either or both of these parameters results in improved speed and high-frequency performance.
For large-scale integrated circuitry, the usual design objectives, in addition to high speed, include high packing density and a simplified fabrication process. Many approaches have been used in an effort to reach these goals, but none appears to have been completely successful. There has therefore been a need for a bipolar transistor construction that provides transistors with improved high-speed performance, while at the same time simplifying the fabrication process and allowing substantially greater device packing densities.
The first-mentioned related application (Ser. No. 600,707) described a solution to this need, but still left room for improvement in the specific device structure.
More particularly, the transistor structure defined in the prior related application includes an emitter region formed to overlap a selected portion of a base region. A wall of insulating material is formed on the base region and adjacent to the edges of the emitter region, and serves to improve the high-speed performance of the device by reducing the length of an inactive base region, and therefore the base resistance. The emitter material in the prior application was described alternatively as semi-insulating polycrystalline silicon (SIPOS) or polycrystalline silicon (poly) appropriately doped to perform the emitter function. Both phosphorous-doped SIPOS and arsenic-doped poly material have separate significant disadvantages when optimum performance is desired from a transistor structure of the type described. Specifically, if phosphorous-doped SIPOS is used as the emitter material, the phosphorous diffuses from the emitter to the base region too rapidly to maintain a thin, heavily doped base region, which is needed for high-speed operation. Also, the use of phosphorous-doped SIPOS as an emitter material results in an irregular common emitter current gain in high-speed transistors.
The use of arsenic-doped poly as the emitter material avoids the problems arising from the use of phosphorous-doped SIPOS, but poses two new ones. First, the injection efficiency is much lower, and therefore the common emitter current gain and overall transistor performance are degraded. Also, there is a tendency for the emitter material to rupture at its periphery during the fabrication process. The injection efficiency is the ratio of the net majority-carrier current across the base-emitter junction to the net minority-carrier current across the same junction. If the injection efficiency is decreased, so is the common emitter current gain for the transistor.
Accordingly, there is a need for improvement in the selection of emitter materials for bipolar transistors for which high speed, packing density, or injection efficiency are considerations. The present invention satisfies this need.